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772 lines
19 KiB
C
772 lines
19 KiB
C
/* $OpenBSD: pcidump.c,v 1.31 2012/05/16 13:01:50 jsg Exp $ */
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/*
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* Copyright (c) 2006, 2007 David Gwynne <loki@animata.net>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/ioctl.h>
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#include <sys/param.h>
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#include <sys/pciio.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcidevs_data.h>
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#include <err.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <paths.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#define PCIDEV "/dev/pci"
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#ifndef nitems
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#define nitems(_a) (sizeof((_a)) / sizeof((_a)[0]))
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#endif
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__dead void usage(void);
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void scanpcidomain(void);
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int probe(int, int, int);
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void dump(int, int, int);
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void hexdump(int, int, int, int);
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const char *str2busdevfunc(const char *, int *, int *, int *);
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int pci_nfuncs(int, int);
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int pci_read(int, int, int, u_int32_t, u_int32_t *);
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int pci_readmask(int, int, int, u_int32_t, u_int32_t *);
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void dump_caplist(int, int, int, u_int8_t);
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void dump_pcie_linkspeed(int, int, int, uint8_t);
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void print_pcie_ls(uint8_t);
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int dump_rom(int, int, int);
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int dump_vga_bios(void);
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__dead void
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usage(void)
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{
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extern char *__progname;
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fprintf(stderr,
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"usage: %s [-v] [-x | -xx | -xxx] [-d pcidev] [bus:dev:func]\n"
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" %s -r file [-d pcidev] bus:dev:func\n",
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__progname, __progname);
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exit(1);
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}
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int pcifd;
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int romfd;
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int verbose = 0;
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int hex = 0;
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int size = 64;
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const char *pci_capnames[] = {
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"Reserved",
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"Power Management",
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"AGP",
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"Vital Product Data (VPD)",
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"Slot Identification",
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"Message Signaled Interrupts (MSI)",
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"CompactPCI Hot Swap",
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"PCI-X",
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"AMD LDT/HT",
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"Vendor Specific",
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"Debug Port",
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"CompactPCI Central Resource Control",
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"PCI Hot-Plug",
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"PCI-PCI",
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"AGP8",
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"Secure",
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"PCI Express",
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"Extended Message Signaled Interrupts (MSI-X)",
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"SATA",
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"PCI Advanced Features"
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};
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int
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main(int argc, char *argv[])
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{
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int nfuncs;
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int bus, dev, func;
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char pcidev[MAXPATHLEN] = PCIDEV;
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char *romfile = NULL;
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const char *errstr;
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int c, error = 0, dumpall = 1, domid = 0;
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while ((c = getopt(argc, argv, "d:r:vx")) != -1) {
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switch (c) {
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case 'd':
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strlcpy(pcidev, optarg, sizeof(pcidev));
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dumpall = 0;
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break;
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case 'r':
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romfile = optarg;
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dumpall = 0;
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break;
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case 'v':
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verbose = 1;
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break;
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case 'x':
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hex++;
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break;
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default:
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usage();
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}
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}
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argc -= optind;
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argv += optind;
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if (argc > 1 || (romfile && argc != 1))
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usage();
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if (romfile) {
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romfd = open(romfile, O_WRONLY|O_CREAT|O_TRUNC, 0777);
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if (romfd == -1)
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err(1, "%s", romfile);
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}
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if (hex > 1)
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size = 256;
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if (hex > 2)
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size = 4096;
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if (argc == 1)
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dumpall = 0;
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if (dumpall == 0) {
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pcifd = open(pcidev, O_RDONLY, 0777);
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if (pcifd == -1)
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err(1, "%s", pcidev);
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} else {
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for (;;) {
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snprintf(pcidev, 16, "/dev/pci%d", domid++);
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pcifd = open(pcidev, O_RDONLY, 0777);
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if (pcifd == -1) {
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if (errno == ENXIO || errno == ENOENT) {
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return 0;
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} else {
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err(1, "%s", pcidev);
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}
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}
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printf("Domain %s:\n", pcidev);
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scanpcidomain();
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close(pcifd);
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}
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}
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if (argc == 1) {
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errstr = str2busdevfunc(argv[0], &bus, &dev, &func);
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if (errstr != NULL)
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errx(1, "\"%s\": %s", argv[0], errstr);
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nfuncs = pci_nfuncs(bus, dev);
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if (nfuncs == -1 || func > nfuncs)
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error = ENXIO;
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else if (romfile)
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error = dump_rom(bus, dev, func);
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else
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error = probe(bus, dev, func);
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if (error != 0)
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errx(1, "\"%s\": %s", argv[0], strerror(error));
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} else {
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printf("Domain %s:\n", pcidev);
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scanpcidomain();
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}
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return (0);
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}
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void
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scanpcidomain(void)
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{
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int nfuncs;
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int bus, dev, func;
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for (bus = 0; bus < 256; bus++) {
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for (dev = 0; dev < 32; dev++) {
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nfuncs = pci_nfuncs(bus, dev);
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for (func = 0; func < nfuncs; func++) {
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probe(bus, dev, func);
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}
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}
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}
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}
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const char *
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str2busdevfunc(const char *string, int *bus, int *dev, int *func)
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{
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const char *errstr;
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char b[80], *d, *f;
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strlcpy(b, string, sizeof(b));
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d = strchr(b, ':');
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if (d == NULL)
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return("device not specified");
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*d++ = '\0';
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f = strchr(d, ':');
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if (f == NULL)
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return("function not specified");
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*f++ = '\0';
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*bus = strtonum(b, 0, 255, &errstr);
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if (errstr != NULL)
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return (errstr);
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*dev = strtonum(d, 0, 31, &errstr);
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if (errstr != NULL)
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return (errstr);
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*func = strtonum(f, 0, 7, &errstr);
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if (errstr != NULL)
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return (errstr);
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return (NULL);
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}
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int
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probe(int bus, int dev, int func)
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{
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u_int32_t id_reg;
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const struct pci_known_vendor *pkv;
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const struct pci_known_product *pkp;
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const char *vendor = NULL, *product = NULL;
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if (pci_read(bus, dev, func, PCI_ID_REG, &id_reg) != 0)
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return (errno);
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if (PCI_VENDOR(id_reg) == PCI_VENDOR_INVALID ||
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PCI_VENDOR(id_reg) == 0)
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return (ENXIO);
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for (pkv = pci_known_vendors; pkv->vendorname != NULL; pkv++) {
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if (pkv->vendor == PCI_VENDOR(id_reg)) {
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vendor = pkv->vendorname;
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break;
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}
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}
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if (vendor != NULL) {
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for (pkp = pci_known_products; pkp->productname != NULL; pkp++)
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if (pkp->vendor == PCI_VENDOR(id_reg) &&
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pkp->product == PCI_PRODUCT(id_reg)) {
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product = pkp->productname;
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break;
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}
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}
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printf(" %d:%d:%d: %s %s\n", bus, dev, func,
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(vendor == NULL) ? "unknown" : vendor,
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(product == NULL) ? "unknown" : product);
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if (verbose)
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dump(bus, dev, func);
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if (hex > 0)
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hexdump(bus, dev, func, size);
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return (0);
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}
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void
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print_pcie_ls(uint8_t speed)
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{
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switch (speed) {
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case 1:
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printf("2.5");
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break;
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case 2:
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printf("5.0");
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break;
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case 3:
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printf("8.0");
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break;
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default:
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printf("unknown (%d)", speed);
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}
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}
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void
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dump_pcie_linkspeed(int bus, int dev, int func, uint8_t ptr)
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{
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u_int32_t creg, sreg;
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u_int8_t cap, cwidth, cspeed, swidth, sspeed;
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if (pci_read(bus, dev, func, ptr + PCI_PCIE_LCAP, &creg) != 0)
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return;
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if (pci_read(bus, dev, func, ptr + PCI_PCIE_LCSR, &sreg) != 0)
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return;
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sreg = sreg >> 16;
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cwidth = (creg >> 4) & 0x3f;
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swidth = (sreg >> 4) & 0x3f;
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cspeed = creg & 0x0f;
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sspeed = sreg & 0x0f;
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if (cwidth == 0)
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return;
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printf("\t Link Speed: ");
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print_pcie_ls(sspeed);
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printf(" / ");
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print_pcie_ls(cspeed);
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printf(" GT/s Link Width: x%d / x%d\n", swidth, cwidth);
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}
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void
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dump_caplist(int bus, int dev, int func, u_int8_t ptr)
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{
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u_int32_t reg;
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u_int8_t cap;
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if (pci_read(bus, dev, func, PCI_COMMAND_STATUS_REG, ®) != 0)
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return;
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if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
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return;
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if (pci_read(bus, dev, func, ptr, ®) != 0)
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return;
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ptr = PCI_CAPLIST_PTR(reg);
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while (ptr != 0) {
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if (pci_read(bus, dev, func, ptr, ®) != 0)
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return;
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cap = PCI_CAPLIST_CAP(reg);
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printf("\t0x%04x: Capability 0x%02x: ", ptr, cap);
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if (cap >= nitems(pci_capnames))
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cap = 0;
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printf("%s\n", pci_capnames[cap]);
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if (cap == PCI_CAP_PCIEXPRESS)
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dump_pcie_linkspeed(bus, dev, func, ptr);
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ptr = PCI_CAPLIST_NEXT(reg);
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}
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}
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void
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dump_type0(int bus, int dev, int func)
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{
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const char *memtype;
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u_int64_t mem;
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u_int64_t mask;
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u_int32_t reg, reg1;
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int bar;
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for (bar = PCI_MAPREG_START; bar < PCI_MAPREG_END; bar += 0x4) {
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if (pci_read(bus, dev, func, bar, ®) != 0 ||
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pci_readmask(bus, dev, func, bar, ®1) != 0)
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warn("unable to read PCI_MAPREG 0x%02x", bar);
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printf("\t0x%04x: BAR ", bar);
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if (reg == 0 && reg1 == 0) {
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printf("empty (%08x)\n", reg);
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continue;
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}
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switch (PCI_MAPREG_TYPE(reg)) {
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case PCI_MAPREG_TYPE_MEM:
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printf("mem ");
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if (PCI_MAPREG_MEM_PREFETCHABLE(reg))
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printf("prefetchable ");
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memtype = "32bit 1m";
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switch (PCI_MAPREG_MEM_TYPE(reg)) {
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case PCI_MAPREG_MEM_TYPE_32BIT:
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memtype = "32bit";
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case PCI_MAPREG_MEM_TYPE_32BIT_1M:
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printf("%s ", memtype);
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printf("addr: 0x%08x/0x%08x\n",
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PCI_MAPREG_MEM_ADDR(reg),
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PCI_MAPREG_MEM_SIZE(reg1));
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break;
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case PCI_MAPREG_MEM_TYPE_64BIT:
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mem = reg;
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mask = reg1;
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bar += 0x04;
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if (pci_read(bus, dev, func, bar, ®) != 0 ||
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pci_readmask(bus, dev, func, bar, ®1) != 0)
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warn("unable to read 0x%02x", bar);
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mem |= (u_int64_t)reg << 32;
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mask |= (u_int64_t)reg1 << 32;
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printf("64bit addr: 0x%016llx/0x%08llx\n",
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PCI_MAPREG_MEM64_ADDR(mem),
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PCI_MAPREG_MEM64_SIZE(mask));
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break;
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}
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break;
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case PCI_MAPREG_TYPE_IO:
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printf("io addr: 0x%08x/0x%04x\n",
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PCI_MAPREG_IO_ADDR(reg),
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PCI_MAPREG_IO_SIZE(reg1));
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break;
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}
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}
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if (pci_read(bus, dev, func, PCI_CARDBUS_CIS_REG, ®) != 0)
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warn("unable to read PCI_CARDBUS_CIS_REG");
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printf("\t0x%04x: Cardbus CIS: %08x\n", PCI_CARDBUS_CIS_REG, reg);
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if (pci_read(bus, dev, func, PCI_SUBSYS_ID_REG, ®) != 0)
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warn("unable to read PCI_SUBSYS_ID_REG");
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printf("\t0x%04x: Subsystem Vendor ID: %04x Product ID: %04x\n",
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PCI_SUBSYS_ID_REG, PCI_VENDOR(reg), PCI_PRODUCT(reg));
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if (pci_read(bus, dev, func, PCI_ROM_REG, ®) != 0)
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warn("unable to read PCI_ROM_REG");
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printf("\t0x%04x: Expansion ROM Base Address: %08x\n",
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PCI_ROM_REG, reg);
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if (pci_read(bus, dev, func, 0x38, ®) != 0)
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warn("unable to read 0x38 (reserved)");
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printf("\t0x%04x: %08x\n", 0x38, reg);
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if (pci_read(bus, dev, func, PCI_INTERRUPT_REG, ®) != 0)
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warn("unable to read PCI_INTERRUPT_REG");
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printf("\t0x%04x: Interrupt Pin: %02x Line: %02x Min Gnt: %02x"
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" Max Lat: %02x\n", PCI_INTERRUPT_REG, PCI_INTERRUPT_PIN(reg),
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PCI_INTERRUPT_LINE(reg), PCI_MIN_GNT(reg), PCI_MAX_LAT(reg));
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}
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void
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dump_type1(int bus, int dev, int func)
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{
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u_int32_t reg;
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int bar;
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for (bar = PCI_MAPREG_START; bar < PCI_MAPREG_PPB_END; bar += 0x4) {
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if (pci_read(bus, dev, func, bar, ®) != 0)
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warn("unable to read PCI_MAPREG 0x%02x", bar);
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printf("\t0x%04x: %08x\n", bar, reg);
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}
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if (pci_read(bus, dev, func, PCI_PRIBUS_1, ®) != 0)
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warn("unable to read PCI_PRIBUS_1");
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printf("\t0x%04x: Primary Bus: %d Secondary Bus: %d "
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"Subordinate Bus: %d \n\t Secondary Latency Timer: %02x\n",
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PCI_PRIBUS_1, (reg >> 0) & 0xff, (reg >> 8) & 0xff,
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(reg >> 16) & 0xff, (reg >> 24) & 0xff);
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if (pci_read(bus, dev, func, PCI_IOBASEL_1, ®) != 0)
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warn("unable to read PCI_IOBASEL_1");
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printf("\t0x%04x: I/O Base: %02x I/O Limit: %02x "
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"Secondary Status: %04x\n", PCI_IOBASEL_1, (reg >> 0 ) & 0xff,
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(reg >> 8) & 0xff, (reg >> 16) & 0xffff);
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if (pci_read(bus, dev, func, PCI_MEMBASE_1, ®) != 0)
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warn("unable to read PCI_MEMBASE_1");
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printf("\t0x%04x: Memory Base: %04x Memory Limit: %04x\n",
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PCI_MEMBASE_1, (reg >> 0) & 0xffff, (reg >> 16) & 0xffff);
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if (pci_read(bus, dev, func, PCI_PMBASEL_1, ®) != 0)
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warn("unable to read PCI_PMBASEL_1");
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printf("\t0x%04x: Prefetch Memory Base: %04x "
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"Prefetch Memory Limit: %04x\n", PCI_PMBASEL_1,
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(reg >> 0) & 0xffff, (reg >> 16) & 0xffff);
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#undef PCI_PMBASEH_1
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#define PCI_PMBASEH_1 0x28
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if (pci_read(bus, dev, func, PCI_PMBASEH_1, ®) != 0)
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warn("unable to read PCI_PMBASEH_1");
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printf("\t0x%04x: Prefetch Memory Base Upper 32 Bits: %08x\n",
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PCI_PMBASEH_1, reg);
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#undef PCI_PMLIMITH_1
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#define PCI_PMLIMITH_1 0x2c
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if (pci_read(bus, dev, func, PCI_PMLIMITH_1, ®) != 0)
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warn("unable to read PCI_PMLIMITH_1");
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printf("\t0x%04x: Prefetch Memory Limit Upper 32 Bits: %08x\n",
|
|
PCI_PMLIMITH_1, reg);
|
|
|
|
#undef PCI_IOBASEH_1
|
|
#define PCI_IOBASEH_1 0x30
|
|
if (pci_read(bus, dev, func, PCI_IOBASEH_1, ®) != 0)
|
|
warn("unable to read PCI_IOBASEH_1");
|
|
printf("\t0x%04x: I/O Base Upper 16 Bits: %04x "
|
|
"I/O Limit Upper 16 Bits: %04x\n", PCI_IOBASEH_1,
|
|
(reg >> 0) & 0xffff, (reg >> 16) & 0xffff);
|
|
|
|
#define PCI_PPB_ROM_REG 0x38
|
|
if (pci_read(bus, dev, func, PCI_PPB_ROM_REG, ®) != 0)
|
|
warn("unable to read PCI_PPB_ROM_REG");
|
|
printf("\t0x%04x: Expansion ROM Base Address: %08x\n",
|
|
PCI_PPB_ROM_REG, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_INTERRUPT_REG, ®) != 0)
|
|
warn("unable to read PCI_INTERRUPT_REG");
|
|
printf("\t0x%04x: Interrupt Pin: %02x Line: %02x "
|
|
"Bridge Control: %04x\n",
|
|
PCI_INTERRUPT_REG, PCI_INTERRUPT_PIN(reg),
|
|
PCI_INTERRUPT_LINE(reg), reg >> 16);
|
|
}
|
|
|
|
void
|
|
dump_type2(int bus, int dev, int func)
|
|
{
|
|
u_int32_t reg;
|
|
|
|
if (pci_read(bus, dev, func, PCI_MAPREG_START, ®) != 0)
|
|
warn("unable to read PCI_MAPREG\n");
|
|
printf("\t0x%04x: Cardbus Control Registers Base Address: %08x\n",
|
|
PCI_MAPREG_START, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_PRIBUS_2, ®) != 0)
|
|
warn("unable to read PCI_PRIBUS_2");
|
|
printf("\t0x%04x: Primary Bus: %d Cardbus Bus: %d "
|
|
"Subordinate Bus: %d \n\t Cardbus Latency Timer: %02x\n",
|
|
PCI_PRIBUS_2, (reg >> 0) & 0xff, (reg >> 8) & 0xff,
|
|
(reg >> 16) & 0xff, (reg >> 24) & 0xff);
|
|
|
|
if (pci_read(bus, dev, func, PCI_MEMBASE0_2, ®) != 0)
|
|
warn("unable to read PCI_MEMBASE0_2\n");
|
|
printf("\t0x%04x: Memory Base 0: %08x\n", PCI_MEMBASE0_2, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_MEMLIMIT0_2, ®) != 0)
|
|
warn("unable to read PCI_MEMLIMIT0_2\n");
|
|
printf("\t0x%04x: Memory Limit 0: %08x\n", PCI_MEMLIMIT0_2, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_MEMBASE1_2, ®) != 0)
|
|
warn("unable to read PCI_MEMBASE1_2\n");
|
|
printf("\t0x%04x: Memory Base 1: %08x\n", PCI_MEMBASE1_2, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_MEMLIMIT1_2, ®) != 0)
|
|
warn("unable to read PCI_MEMLIMIT1_2\n");
|
|
printf("\t0x%04x: Memory Limit 1: %08x\n", PCI_MEMLIMIT1_2, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_IOBASE0_2, ®) != 0)
|
|
warn("unable to read PCI_IOBASE0_2\n");
|
|
printf("\t0x%04x: I/O Base 0: %08x\n", PCI_IOBASE0_2, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_IOLIMIT0_2, ®) != 0)
|
|
warn("unable to read PCI_IOLIMIT0_2\n");
|
|
printf("\t0x%04x: I/O Limit 0: %08x\n", PCI_IOLIMIT0_2, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_IOBASE1_2, ®) != 0)
|
|
warn("unable to read PCI_IOBASE1_2\n");
|
|
printf("\t0x%04x: I/O Base 1: %08x\n", PCI_IOBASE1_2, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_IOLIMIT1_2, ®) != 0)
|
|
warn("unable to read PCI_IOLIMIT1_2\n");
|
|
printf("\t0x%04x: I/O Limit 1: %08x\n", PCI_IOLIMIT1_2, reg);
|
|
|
|
if (pci_read(bus, dev, func, PCI_INTERRUPT_REG, ®) != 0)
|
|
warn("unable to read PCI_INTERRUPT_REG");
|
|
printf("\t0x%04x: Interrupt Pin: %02x Line: %02x "
|
|
"Bridge Control: %04x\n",
|
|
PCI_INTERRUPT_REG, PCI_INTERRUPT_PIN(reg),
|
|
PCI_INTERRUPT_LINE(reg), reg >> 16);
|
|
|
|
if (pci_read(bus, dev, func, PCI_SUBVEND_2, ®) != 0)
|
|
warn("unable to read PCI_SUBVEND_2");
|
|
printf("\t0x%04x: Subsystem Vendor ID: %04x Product ID: %04x\n",
|
|
PCI_SUBVEND_2, PCI_VENDOR(reg), PCI_PRODUCT(reg));
|
|
|
|
if (pci_read(bus, dev, func, PCI_PCCARDIF_2, ®) != 0)
|
|
warn("unable to read PCI_PCCARDIF_2\n");
|
|
printf("\t0x%04x: 16-bit Legacy Mode Base Address: %08x\n",
|
|
PCI_PCCARDIF_2, reg);
|
|
}
|
|
|
|
void
|
|
dump(int bus, int dev, int func)
|
|
{
|
|
u_int32_t reg;
|
|
u_int8_t capptr = PCI_CAPLISTPTR_REG;
|
|
|
|
if (pci_read(bus, dev, func, PCI_ID_REG, ®) != 0)
|
|
warn("unable to read PCI_ID_REG");
|
|
printf("\t0x%04x: Vendor ID: %04x Product ID: %04x\n", PCI_ID_REG,
|
|
PCI_VENDOR(reg), PCI_PRODUCT(reg));
|
|
|
|
if (pci_read(bus, dev, func, PCI_COMMAND_STATUS_REG, ®) != 0)
|
|
warn("unable to read PCI_COMMAND_STATUS_REG");
|
|
printf("\t0x%04x: Command: %04x Status ID: %04x\n",
|
|
PCI_COMMAND_STATUS_REG, reg & 0xffff, (reg >> 16) & 0xffff);
|
|
|
|
if (pci_read(bus, dev, func, PCI_CLASS_REG, ®) != 0)
|
|
warn("unable to read PCI_CLASS_REG");
|
|
printf("\t0x%04x: Class: %02x Subclass: %02x Interface: %02x "
|
|
"Revision: %02x\n", PCI_CLASS_REG, PCI_CLASS(reg),
|
|
PCI_SUBCLASS(reg), PCI_INTERFACE(reg), PCI_REVISION(reg));
|
|
|
|
if (pci_read(bus, dev, func, PCI_BHLC_REG, ®) != 0)
|
|
warn("unable to read PCI_BHLC_REG");
|
|
printf("\t0x%04x: BIST: %02x Header Type: %02x Latency Timer: %02x "
|
|
"Cache Line Size: %02x\n", PCI_BHLC_REG, PCI_BIST(reg),
|
|
PCI_HDRTYPE(reg), PCI_LATTIMER(reg), PCI_CACHELINE(reg));
|
|
|
|
switch (PCI_HDRTYPE_TYPE(reg)) {
|
|
case 2:
|
|
dump_type2(bus, dev, func);
|
|
capptr = PCI_CARDBUS_CAPLISTPTR_REG;
|
|
break;
|
|
case 1:
|
|
dump_type1(bus, dev, func);
|
|
break;
|
|
case 0:
|
|
dump_type0(bus, dev, func);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
dump_caplist(bus, dev, func, capptr);
|
|
}
|
|
|
|
void
|
|
hexdump(int bus, int dev, int func, int size)
|
|
{
|
|
u_int32_t reg;
|
|
int i;
|
|
|
|
for (i = 0; i < size; i += 4) {
|
|
if (pci_read(bus, dev, func, i, ®) != 0) {
|
|
if (errno == EINVAL)
|
|
return;
|
|
warn("unable to read 0x%02x", i);
|
|
}
|
|
|
|
if ((i % 16) == 0)
|
|
printf("\t0x%04x:", i);
|
|
printf(" %08x", reg);
|
|
|
|
if ((i % 16) == 12)
|
|
printf("\n");
|
|
}
|
|
}
|
|
|
|
int
|
|
pci_nfuncs(int bus, int dev)
|
|
{
|
|
u_int32_t hdr;
|
|
|
|
if (pci_read(bus, dev, 0, PCI_BHLC_REG, &hdr) != 0)
|
|
return (-1);
|
|
|
|
return (PCI_HDRTYPE_MULTIFN(hdr) ? 8 : 1);
|
|
}
|
|
|
|
int
|
|
pci_read(int bus, int dev, int func, u_int32_t reg, u_int32_t *val)
|
|
{
|
|
struct pci_io io;
|
|
int rv;
|
|
|
|
bzero(&io, sizeof(io));
|
|
io.pi_sel.pc_bus = bus;
|
|
io.pi_sel.pc_dev = dev;
|
|
io.pi_sel.pc_func = func;
|
|
io.pi_reg = reg;
|
|
io.pi_width = 4;
|
|
|
|
rv = ioctl(pcifd, PCIOCREAD, &io);
|
|
if (rv != 0)
|
|
return (rv);
|
|
|
|
*val = io.pi_data;
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
pci_readmask(int bus, int dev, int func, u_int32_t reg, u_int32_t *val)
|
|
{
|
|
struct pci_io io;
|
|
int rv;
|
|
|
|
bzero(&io, sizeof(io));
|
|
io.pi_sel.pc_bus = bus;
|
|
io.pi_sel.pc_dev = dev;
|
|
io.pi_sel.pc_func = func;
|
|
io.pi_reg = reg;
|
|
io.pi_width = 4;
|
|
|
|
rv = ioctl(pcifd, PCIOCREADMASK, &io);
|
|
if (rv != 0)
|
|
return (rv);
|
|
|
|
*val = io.pi_data;
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
dump_rom(int bus, int dev, int func)
|
|
{
|
|
struct pci_rom rom;
|
|
u_int32_t cr, addr;
|
|
|
|
if (pci_read(bus, dev, func, PCI_ROM_REG, &addr) != 0 ||
|
|
pci_read(bus, dev, func, PCI_CLASS_REG, &cr) != 0)
|
|
return (errno);
|
|
|
|
if (addr == 0 && PCI_CLASS(cr) == PCI_CLASS_DISPLAY &&
|
|
PCI_SUBCLASS(cr) == PCI_SUBCLASS_DISPLAY_VGA)
|
|
return dump_vga_bios();
|
|
|
|
bzero(&rom, sizeof(rom));
|
|
rom.pr_sel.pc_bus = bus;
|
|
rom.pr_sel.pc_dev = dev;
|
|
rom.pr_sel.pc_func = func;
|
|
if (ioctl(pcifd, PCIOCGETROMLEN, &rom))
|
|
return (errno);
|
|
|
|
rom.pr_rom = malloc(rom.pr_romlen);
|
|
if (rom.pr_rom == NULL)
|
|
return (ENOMEM);
|
|
|
|
if (ioctl(pcifd, PCIOCGETROM, &rom))
|
|
return (errno);
|
|
|
|
if (write(romfd, rom.pr_rom, rom.pr_romlen) == -1)
|
|
return (errno);
|
|
|
|
return (0);
|
|
}
|
|
|
|
#define VGA_BIOS_ADDR 0xc0000
|
|
#define VGA_BIOS_LEN 0x10000
|
|
|
|
int
|
|
dump_vga_bios(void)
|
|
{
|
|
#if defined(__amd64__) || defined(__i386__)
|
|
void *bios;
|
|
int fd;
|
|
|
|
fd = open(_PATH_MEM, O_RDONLY, 0777);
|
|
if (fd == -1)
|
|
err(1, "%s", _PATH_MEM);
|
|
|
|
bios = malloc(VGA_BIOS_LEN);
|
|
if (bios == NULL)
|
|
return (ENOMEM);
|
|
|
|
if (pread(fd, bios, VGA_BIOS_LEN, VGA_BIOS_ADDR) == -1)
|
|
err(1, "%s", _PATH_MEM);
|
|
|
|
if (write(romfd, bios, VGA_BIOS_LEN) == -1)
|
|
return (errno);
|
|
|
|
return (0);
|
|
#else
|
|
return (ENODEV);
|
|
#endif
|
|
}
|